Designers of integrated circuit devices (“chips”), generally application-specific integrated circuits (“ASICs”), use prototyping as part of the electronic design automation process prior to manufacture of the chip. Prototyping is one type of hardware-based functional verification that allows the circuit designer to observe the behavior of the circuit design under conditions approximating its final, manufactured performance. During prototyping, a circuit design, generally written in register transfer language (“RTL”) code, is programmed into one or more programmable logic chips, frequently field-programmable gate arrays (“FPGA”) on a prototyping board. FPGA-based prototypes are a fully functional representation of the circuit design, its circuit board, and its input/output (“I/O”) devices. Also, FPGA prototypes generally run at speeds much closer to the clock speed at which the manufactured chip will run than other types of functional verification, e.g., software simulation, thereby allowing for verifying the circuit design under many more conditions in the same amount of time than other verification methods, and in particular, software simulation. The circuit design prototype may also be operated in another electronic circuit, e.g., the electronic circuit for which the design under verification will be used after fabrication, so that the circuit design prototype may be observed and tested in an environment in which the manufactured chip will be used. As such, circuit designers may use FPGA prototyping as a vehicle for software co-development and validation, increasing the speed and accuracy of system developments.
Prototyping of a circuit design using programmable logic chips (e.g., FPGAs) can have advantages over other types of functional verification, namely emulation using a plurality of emulation processors. First, prototyping using programmable logic chips generally results in higher speed relative to emulation using emulation processors. Second, such higher-speed circuit design prototypes using programmable logic chips can sometimes even run in real-time, that is, the prototype may run at the intended clock speed of the manufactured chip, rather than a reduced clock speed. This is not always the case, notably for higher performance circuit designs that have clock speeds higher than the maximum allowed by the programmable logic chips. Third, such prototyping systems using programmable logic chips are generally of lower cost than an emulation system using processors.
Exemplary hardware used in prototyping comprises FPGAs or other types of programmable logic chips, input/output circuitry, and interconnect circuitry connecting the programmable logic chips to each other and to the input-output circuitry. An example of commercial prototyping hardware includes the DN7006K1 OPCIe-8T manufactured by the DINI Group of La Jolla, Calif. The DN7006K10PCIe-8T features six Altera Stratix 3 3SL340 (FF1760) FPGAs, a configuration FPGA, global clock generation hardware, interconnect connecting the FPGAs to each other, input/output devices including an eight lane PCI Express Endpoint, and DDR SODIMM slots for the insertion of RAM.
To enable a circuit designer to evaluate the circuit design prototype, FPGAs are generally embedded with an internal logic analyzer circuit that can capture and store logic signals during operation. Each internal logic analyzer can be triggered on a combination of multiple signals from the user logic. Once these signals are captured, the internal logic analyzer can unload the data through an interface to a computer. Typically, an interface is connected between the computer and the FPGA where the computer can arm the internal logic analyzer and poll it until a data acquisition has been made. While internal logic analyzers work well for debugging logic of each individual FPGA, existing designs have limitations for multiple FPGA systems. Specifically, each logic analyzer captures data waveforms for its respective FPGA independently of the other FPGAs in the system. This design limitation leads to confusion and loss of correct and efficient debugging for circuit design prototypes that include multiple FPGAs.